Fully ion implanted junction field effect transistor

ABSTRACT

A method of making a planar junction field-effect transistor in which a semi-insulating substrate of a III-V semiconductor, particularly InP, is ion implanted by two ions to produce both an n-type region and a p-type region. The gate is further defined by selectively etching through the gate-implant region to the source/drain channel.

This application is a continuation, of applicaiton Ser. No. 471,096, filed Mar. 1, 1983, now abandoned.

BACKGROUND

1. Field of the Invention

This invention pertains generally to field-effect transistors (FETs) and in particular to junction FETs made by ion implantation from III-V semiconductors.

2. Prior Art

Present-day semiconductor electronics is dominated by silicon technology. However, it is recognized that other semiconducting materials, though lacking silicon's technological maturity, offer the promise of improved speed and performance.

In a microwave FET, the velocity of the charge carriers and parastic elements play important roles in determining its high frequency performance. At low electric fields, charge carrier velocity is proportional to the electric field with the proportionality constant being the drift mobility. However, at higher electric fields the relationship becomes non linear. For Si, the drift velocity reaches a saturation value at fields above 5×10⁴ V/cm. For GaAs and InP, the drift velocity first reaches a peak and then declines to a saturation value. Since the low-field mobility of silicon is relatively small, the performance of GaAs and InP is expected to be superior to that of Si. InP is expected to operate at higher frequencies than GaAs due to its higher peak velocity. In addition, the higher reverse breakdown voltage and higher thermal conductivity of InP also gives it the potential for outperforming GaAs.

Early device designers, faced with the choice of GaAs, InP and other III-V compounds besides GaAs and InP, picked GaAs because of its perceived technological advantages. The primary FET structure for GaAs is the metal-semiconductor field-effect transistor (MESFET). MESFETs made from GaAs are relatively easy to fabricate because of the large Schottky barrier between the metal and the semiconductor. However, the Schottky barrier for InP and III-V alloys such as InGaAs is too small to easily fabricate Schottky barrier FETs. Thus InP and InGaAs were not extensively pursued for use in FETs.

A junction gate structure in InP circumvents the Schottky barrier problem and early work on diffused JFETs (surface diffusion using Zn dopants) have been reported. Ion implantation of the dopants is an attractive alternative approach since it is highly compatible with the fabrication of planar devices and monolithic circuits. Ion implantation has been used to make FETs from InP but these efforts have been limited to MESFETs. The inventor participated in research leading to the present invention that resulted in a doubly ion implanted InP JFET. However, this device needed to be isolated by an etch which created a mesa structure on which it was difficult to deposit interconnect lines.

SUMMARY OF THE INVENTION

Therefore it is an object of this invention to provide a high frequency field-effect transistor.

It is a further object of this invention to provide a junction field-effect transistor made of III-V semiconducting materials.

It is yet a further object of this invention to provide a simple method of making III-V junction field-effect transistors.

This invention is a method of making a planar JFET from III-V compounds and alloys in which both the n-region and p-regions are ion implanted in a semi-insulating substrate and in which the gate is further defined by selectively etching through the gate-implant region to the source/drain channel.

In one embodiment, InP was used as the substrate, ²⁸ Si was implanted in the source and drain, and ⁹ Be was implanted in the gate region. Plasma etching defined a 1 micrometer gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of the substrate and undefined barrier layer from which the JFET is made.

FIG. 2 is a cross-sectional view of the JFET following the first ion implantation.

FIG. 3 is a cross-sectional view of the JFET following the second ion implantation.

FIG. 4 is a cross-sectional view of the JFET following deposition of the gate metal.

FIG. 5 is a cross-sectional view of the JFET following the deposition of the source/drain metal.

FIG. 6 is a cross-sectional view of the JFET following the gate definition etch.

DETAILED DESCRIPTION OF THE INVENTION

Junction field-effect transistors (JFETs) can be easily fabricated in a planar geometry from InP and other III-V semiconductors by double ion implantations which establish both the p-region and the n-region. Although the procedure is set forth in the context of a device made of InP the procedure is quite general and is not limited to InP. In addition, although the example is limited to a discrete device it is readily understood that multiple devices can be fabricated on a single chip to form an integrated circuit.

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIG. 1 thereof, the JFET fabrication uses a substrate 10 of InP grown by the liquid encapsulated Czochralski method that is Fe-doped to be semi-insulating of resistivity greater than 10⁷ ohm-cm. The surface of the InP substrate has a (100)-orientation. In a first processing step of creating an n-type active region, the substrate is first cleaned with organic solvents and etched in a 1:4 HIO₃ :H₂ O solution. Then a 500 nm thick barrier layer 12 of Si₃ N₄ is deposited on the (100) surface of the substrate 10. Alternative materials for the barrier 12 are SiO₂ or other etchable material.

Thereafter, photoresist is deposited on the barrier layer 12 and photolithographically patterned to leave only photoresist portions 14 and 16 as illustrated in cross-sectional view in FIG. 2. The photoresist then acts as a mask when a plasma etching step removes all the exposed barrier layer but leaves the barrier layer portions 18 and 20.

Then the wafer is ion implanted. The combination of photoresist portions 14 and 16 and barrier portions 18 and 20 serves as a mask so that only an initial active region 22 is implanted in an area 50 micrometers long and 300 micrometers wide. The initial ion implant is chosen to be ²⁸ Si (isotopic silicon of atomic mass 28) so that the doping in the initial active region 22 is n-type. Two separate implant schedules are used: 9.4×10¹² cm⁻² at 580 keV, 4.6×10¹² cm⁻² at 280 keV and 7.0×10¹² cm⁻² at 580 keV, 3.5×10¹² cm⁻² at 280 keV. The first parameter is the surface density of the implanted ion and the second parameter is the energy of the ion. These implant schedules correspond to calculated atomic concentrations of ²⁸ Si in the initial active region 22 of 2.5×10¹⁷ cm⁻³ and 1.9×10¹⁷ cm⁻³ respectively. The residual substrate 26 that was not implanted is left semi-insulating. The remaining photoresist portions 14 and 16 are then removed.

In a second step of creating a p type region from which a gate is formed, new photoresist is applied in a pattern that defines a channel mask 28 and 30 as illustrated in cross section in FIG. 3. The aperture in the mask is 7 micrometers long. The wafer is then etched in a 1:4 HIO₃ :H₂ O for 30 sec to remove 50 nm of InP from the initial active region 22. This etching time is experimentally determined to yield the desired I_(DSS) levels in the finished devices. Alternatively the I_(DSS) levels can be controlled by varying the parameters of the ⁹ Be implant of the implantation step to follow. The etching step further cleans the surface preparatory to the ⁹ Be implant and provides registration marks for later processing steps. The barrier portions 18 and 20 are left to serve as additional registration and to insure that the final p-implant overlays the n-implant over the entire width of the active region 34. The p-implant was accomplished by implanting ⁹ Be at a dose of 6×10¹³ cm⁻² at 30 keV resulting in an n-type extended gate region 32 extending part way into the active region 34. The thickness of the n-type active region 34 is thus reduced and the active region 34 can be considered to be divided into three parts, as shown in cross-sectional view in FIG. 4, a source end 36, a drain end 38, and a source/drain channel 40 connecting those ends. Subsequent to the ion implantation the photoresist 28 and 30 is removed by rinsing the wafer with acetone and the barrier portions 18 and 20 of Si₃ N₄ are stripped by immersion in HF.

When silicon or beryllium is implanted in InP, the chip needs to be annealed after the implant for two reasons. First the implantation produces structural damage to the crystalline InP which needs to be annealed out. Secondly in an annealing step the Be or Si diffuses to the desired lattice locations so that the implanted dopant will be activated.

Unfortunately in a straight-forward anneal of III-V compounds with the surface exposed, the Group V elements tend to dissociate from the surface thus producing a non-stoichiometric III-V semiconductor. Two techniques are commonly available to overcome the dissociation problem. In the first method, the III-V material is coated with a layer of SiO₂ or Si₃ N₄ prior to the anneal. However during the anneal cracking of the SiO₂ or Si₃ N₄ due to thermal stress and possible Si out-diffusion can occur. The second method, called a capless anneal, requires annealing in an over pressure of PH₃ (phosphene) or AsH₃. Unfortunately both these gases are toxic and thus undesirable in a production environment.

Yet another method has been developed which avoids these problems in what is called a proximity or close-contact anneal. The proximity anneal is accomplished by sandwiching the InP wafer between two silicon wafers coated on the InP side with Si₃ N₄. The sandwich is then raised to the annealing temperature. The Group V phosphorus dissociates only to the extent that the small void between the InP and the Si₃ N₄ coating is saturated with phosphorus. The proximity anneal is performed at 700° C. for 15 minutes.

In a third step of placing contacts for the source, gate and drain, the gate is defined by depositing by evaporation a gate metal first layer 42 and second layer 44. Note that these layers have not been drawn to scale in FIG. 4. The gate is placed as close as possible within processing limits to the source end 36 in order to minimize the source-gate resistance. The gate metal first layer 42 consists of AuZn in proportions of 95:5 wt % and is 50 nm thick. The gate metal second layer 44 consists of Au of 350 nm thickness. The first layer 42 and second layer 44 of the gate metal are then commonly defined by conventional photoresist lift-off techniques. Both layers 42 and 44 of the gate metal are 1 micrometers long by 300 micrometers wide in the direction transverse to the cross-section of FIG. 4.

The source/drain contacts are defined by another photolithographic step as illustrated in cross-section in FIG. 5. First layer source and drain metals 46 and 48 are deposited of eutectic AuGe, i.e. in proportions of 88:12 wt % to a thickness of 100 nm. Then second layer source and drain metals 50 and 52 of Au are deposited to a thickness of 100 nm.

In a fourth step of solating the gate region, the structural definition is completed by a Cl₂ plasma etch which, as illustrated in FIG. 6, completely etches away the exposed p-type InP. The Cl₂ etch proceeds until the reverse gate source I-V characteristic shows low leakage current and a sharp breakdown. The etch leaves only a 1 micrometer long by 300 micrometer wide junction gate 54 overlaying the source/drain channel 40 of the active region 34.

In a fifth and final step, all the metal contacts are alloyed in a forming gas atmosphere at 400° C. for 45 sec. The effect of the elevated temperature is to drive the Ge from the first layer source/drain metals 46 and 48 into the active region 34 and the Zn from the first layer gate metal 42 into the Junction gate 54 thus forming ohmic contacts with the n type and p-type InP.

Metallic interconnects can be deposited on a chip containing many of the devices described above so as to produce an integrated circuit. The JFET is essentially planar so there are no steep steps presenting coverage problems to an interconnect deposition. The only two etches in the final JFET which affect the planarity are the minor one between implants which can be replaced by a more systematic immplant and the gate etch which exposes the channel over which interconnects would not be placed. Neither etch creates a steep edge over which an interconnect would be deposited.

The JFET can be improved by an additional implantation of ²⁸ Si into the source end 36 and drain end 38 as illustrated in FIG. 4. A high dose will turn these ends 36 and 38 into n⁺ thereby facilitating the making of ohmic contacts to each and more importantly reducing the source-drain resistance. The low resistance leads to higher frequency performance.

A InP JFET built according to the foregoing description with a gate length of 1 micrometer, a gate width of 300 micrometer, and a source-drain length of 7 micrometer had I_(DSS) =100 mA, i.e. saturated drain current, for V_(G) =0. The maximum mutual transconductance G_(m) is measured to be 8 mS. The gate-source breakdown voltage is found to be 25 V. The device when tested for RF response demonstrates a maximum available gain of 12 dB at 4 GHz, V_(DS) =12 V and V_(G) =2.1 V. At 6 GHz, V_(DS) =9 V and V_(G) =5 V, the maximum available gain is measured to be 5.5 dB. Improvements in performance are to be expected if the processing parameters were optimized. The optimizing procedure has not yet attempted.

Although a fabrication of an InP JFET has been described, it is to be appreciated that a doubly ion implanted JFET is not limited to InP. The same invention is expected to be particularly useful with InGaAs, an alloy of III-V materials useful for high speed electronics. InGaAs, like InP, exhibits a low Schottky barrier which renders difficult the task of building InGaAs MESFETs. The alloys InGa_(1-x) As with x between 0.35 and 0.65 are expected to be useful for high speed devices. An alloy of the composition In₀.53 Ga₀.47 As is particularly useful because of both its speed and its lattice match to InP so that it can be easily grown epitaxially on InP. Yet another favorable III-V alloy is the quatermary alloy. InGaAsP, more accurately written as In_(1-x) Ga_(x) As_(y) P_(1-y). This alloy can be lattice matched over a wide range of alloying. For this invention any of the alloys need to be made semi-insulating, either during growth or during subsequent processing.

Obviously, additional modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein. 

What is claimed and desired to be secured by Letters Patent of the United States is:
 1. A field-effect transistor, comprising:a residual substrate essentially consisting of semi-insulating InP; an active region essentially consisting of n-type InP doped with Si, the source end and drain end of which have a surface substantially co-planar with the surface of the residual substrate and which are connected by a source/drain channel part of said active region the upper surface of which is recessed below the surface of said source end and said drain end; a gate consisting of p-type InP doped with Be oerlaying a portion of said source/drain channel but not the entire source/drain channel and contacting said source/drain channel on only one side, a gate contact comprising Au-Zn overlaying said gate; a drain contact comprising eutectic AuGe overlaying said drain end; and a source contact comprising eutectic AuGe overlaying said source end. 